// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2010 by Lattice Semiconductor Corporation
// --------------------------------------------------------------------
//
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.
//
// --------------------------------------------------------------------
//           
//                     Lattice Semiconductor Corporation
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//                     web: http://www.latticesemi.com/
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//
// --------------------------------------------------------------------
//
//  Project:           7:1 LVDS Video Interface
//  File:              Passthru_Demo_7_to_1_LVDS_TOP.v
//  Title:             Passthru_Demo_7_to_1_LVDS_TOP
//  Description:       Top level design file of passthru demo reference design
//
// --------------------------------------------------------------------
// Code Revision History :
// --------------------------------------------------------------------
// Ver: | Author   | Mod. Date  | Changes Made:
// V1.0 | shossner | 2010-04-25 | Initial Release
//
// --------------------------------------------------------------------

`timescale 1 ns/ 1 ps

module Passthru_Demo_7_to_1_LVDS_TOP 
     (
     
      // Tx module ports
      GSRN,

      TCLK_out,
      TA_out,
      TB_out,
      TC_out,
      TD_out,

      // Rx module ports
      RCLK_in,
      RA_in,
      RB_in,
      RC_in,
      RD_in,
      
      // Status/Debug ports
      SWDIP,
      LED

     );

      
input        GSRN    ;     // Tx module resetn
      // Rx module ports  
input        RCLK_in;      // LVDS clock input pair 
input        RA_in  ;      // LVDS data input pair a
input        RB_in  ;      // LVDS data input pair b
input        RC_in  ;      // LVDS data input pair c
input        RD_in  ;      // LVDS data input pair d
      // Tx module ports
output       TCLK_out;     // LVDS clock output pair 
output       TA_out  ;     // LVDS data output pair a
output       TB_out  ;     // LVDS data output pair b
output       TC_out  ;     // LVDS data output pair c
output       TD_out  ;     // LVDS data output pair d
                          

      // Status/Debug ports
input  [3:0] SWDIP  ;       // 4-DIP Switch
output [3:0] LED    ;       // 4 LEDs


   
// <LVDS cable>                             <LVDS cable>
//            ___          ___         ___          
//  RA_in    |   | rx_a   |   | tx_a  |   |   TA_out
// =========>|   |======> | R |======>|   |=========>
//           |   |        | G |       |   |         
//           |   |        | B |       |   |         
//  RB_in    |   | rx_b   |   | tx_b  |   |   TB_out
// =========>|   |======> | T |======>|   |=========>
//           | R |        | r |       | T |         
//           | x |        | a |       | x |         
//  RC_in    |   | rx_c   | n | tx_c  |   |   TC_out
// =========>|   |======> | s |======>|   |=========>
//           |   |        | f |       |   |         
//           |   |        | o |       |   |         
//  RD_in    |   | rx_d   | r | tx_d  |   |   TD_out
// =========>|   |======> | m |======>|   |=========>
//           |   |        |   |       |   |         
//           |   |------->|>__|       |   |         
//  RCLK_in  |   | RCLK_in            |   | TCLK_out
// =========>|   |------------------->|>  |=========>
//           |   |              eclk  |   |         
//           |___|                    |___|         

   // 7-bit parallel data received by Rx module
   wire [6:0] rx_a;
   wire [6:0] rx_b;
   wire [6:0] rx_c;
   wire [6:0] rx_d;
   wire [6:0] RCLK_out;
   wire       rxpll_lock;              
   wire       dphase_lock;
   wire [3:0] dphase;

   // RGB rcv data
   wire [7:0] r_R;  // Red,   8-bit data depth
   wire [7:0] r_G;  // Green, 8-bit data depth
   wire [7:0] r_B;  // Blue,  8-bit data depth
   wire       r_Vsync;
   wire       r_Hsync;
   wire       r_DE   ;

   // RGB tx data
   wire [7:0] t_R;  // Red,   8-bit data depth
   wire [7:0] t_G;  // Green, 8-bit data depth
   wire [7:0] t_B;  // Blue,  8-bit data depth
   wire       t_Vsync;
   wire       t_Hsync;
   wire       t_DE   ;

   // 7-bit parallel data ready to be transmited by Tx module
   wire [6:0] tx_a;
   wire [6:0] tx_b;
   wire [6:0] tx_c;
   wire [6:0] tx_d;

   wire       RST;   
   
   wire       sclk;
   wire       eclk;
   wire       stop;


   assign RST = ~ GSRN;
   
                                           
   //--------------------------------------------------------------------
   //-- Rx module
   //--------------------------------------------------------------------

  
   LVDS_7_to_1_RX rx_inst 
                  (
                   .dphase_sel  (1'b0),
                   .dphase_in   (4'b0),                  
                   .RCLK_in     (RCLK_in),  // LVDS clock input pair
                   .R0_in       (RA_in),    // LVDS data input pair 0
                   .R1_in       (RB_in),    // LVDS data input pair 1
                   .R2_in       (RC_in),    // LVDS data input pair 2
                   .R3_in       (RD_in),    // LVDS data input pair 3
                                
                   .RCLK_out    (RCLK_out), // 7-bit parallel clock word
                   .R0_out      (rx_a),     // 7-bit data output 0
                   .R1_out      (rx_b),     // 7-bit data output 1
                   .R2_out      (rx_c),     // 7-bit data output 2
                   .R3_out      (rx_d),     // 7-bit data output 3
                   .sclk        (sclk),     // parallel clock out

                   .rxpll_lock  (rxpll_lock),              
                   .eclk        (eclk),     // 3.5x clock from PLL
                   .stop        (stop),     // eclksynca control signal out
                   .dphase_lock (dphase_lock),
                   .dphase_out  (dphase)
                  );




// Pin mapping from [rx_a, rx_b, rx_c, rx_d] to [r_R, r_G, r_B]
//                  bit-7     bit-6     bit-5     bit-4     bit-3     bit-2     bit-1     bit-0
   assign  r_R = { rx_a[5] , rx_a[6] , rx_d[1] , rx_d[2] , rx_d[3] , rx_d[4] , rx_d[5] , rx_d[6] };
   assign  r_G = { rx_a[3] , rx_a[4] , rx_c[2] , rx_c[3] , rx_c[4] , rx_c[5] , rx_c[6] , rx_d[0] };
   assign  r_B = { rx_a[1] , rx_a[2] , rx_b[3] , rx_b[4] , rx_b[5] , rx_b[6] , rx_c[0] , rx_c[1] };
// note: bit0 is received first in XO2 7:1 primitives

   assign  r_Vsync = rx_b[1];
   assign  r_Hsync = rx_b[2];
   assign  r_DE    = rx_b[0];


   //--------------------------------------------------------------------
   //-- RGB transform module
   //--------------------------------------------------------------------
   
    RGB_transform RGB_trans (
        .clk    (sclk),
        .rst    (RST),
        .sel    (SWDIP),
        .R_in   (r_R),
        .G_in   (r_G),
        .B_in   (r_B),
        .DE_in  (r_DE),
        .HS_in  (r_Hsync),
        .VS_in  (r_Vsync),
        .R_out  (t_R),
        .G_out  (t_G),
        .B_out  (t_B),
        .DE_out (t_DE),
        .HS_out (t_Hsync),
        .VS_out (t_Vsync)
    );


// Pin mapping from [t_R, t_G, t_B] to [tx_a, tx_b, tx_c, tx_d]
//                  bit-6    bit-5    bit-4    bit-3    bit-2      bit-1    bit-0
   assign  tx_a = { t_R[6] , t_R[7] , t_G[6] , t_G[7] , t_B[6]  , t_B[7]  , 1'b1   };
   assign  tx_b = { t_B[2] , t_B[3] , t_B[4] , t_B[5] , t_Hsync , t_Vsync , t_DE   };
   assign  tx_c = { t_G[1] , t_G[2] , t_G[3] , t_G[4] , t_G[5]  , t_B[0]  , t_B[1] };
   assign  tx_d = { t_R[0] , t_R[1] , t_R[2] , t_R[3] , t_R[4]  , t_R[5]  , t_G[0] };
// note: bit0 is transmitted first in XO2 7:1 primitives

   //--------------------------------------------------------------------
   //-- Tx module
   //--------------------------------------------------------------------
   
   LVDS_7_to_1_TX tx_inst
                  (
                   .RST_Tx   (RST),       // Tx module reset      
                   .eclk     (eclk),      // 3.5x clock for serializer
                   .clk_s    (sclk),      // slow clock for eclksynca reset
                   .stop     (stop),      // eclksynca control signal in
                                          
                   .T0_in    (tx_a),      // 7-bit data input 0
                   .T1_in    (tx_b),      // 7-bit data input 1
                   .T2_in    (tx_c),      // 7-bit data input 2
                   .T3_in    (tx_d),      // 7-bit data input 3
                             
                   .TCLK_out (TCLK_out),  // LVDS clock output pair 
                   .T0_out   (TA_out),    // LVDS data output pair 0
                   .T1_out   (TB_out),    // LVDS data output pair 1
                   .T2_out   (TC_out),    // LVDS data output pair 2
                   .T3_out   (TD_out)     // LVDS data output pair 3
                  );
    
 
   // Connecting signals out for status checking, asserted low 
   
 assign LED = {~dphase_lock, ~dphase[2:0]};
   

                
endmodule

      
